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Center for Electronic System Level Design & Verification |
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Increasing design complexity and shorter time-to-market (TTM) has been the mantra of modern day electronic systems. This challenge has led to many innovative solutions being explored including rise in design abstraction level, developing suitable methodology, tools, language, etc. This has opened many opportunities to academicians, technologists, EDA companies, Service companies and the like to seek innovative solutions.
The research focus at the Center for Electronic System Level Design & Verification (CESLDV) would include but is not restricted to the following:
- To explore alternate seamless design flow to support ESL design & Verification at abstraction levels beyond RTL.
- Bring about the awareness regarding this change in methodology by offering various courses to the academia and industry.
- Pursue industry consultation by providing feasible solution to reduce design cycle time thereby shorter time to market resulting in higher profits.
- Become the IP warehouse by developing IP’s at various levels of abstraction.
- Participate and Conduct regular conferences in relevant areas.
- Explore the impact of Multi-core and Network-On-Chip (NOC) on next generation systems.
- Develop innovative verification flow for ESL to reduce TTM.
- Promote and work on various System level languages including SystemC, SystemVerilog, etc.
- Migrating/adapting from/with legacy methodologies with proposed state-of-art methodology.
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